first version of the diagram synthesis

teetime.configuration.dsl.klighd/src/teetime/configuration/dsl/klighd/ConfigurationDiagramSynthesis.xtend

 package teetime.configuration.dsl.klighd
 
+import de.cau.cs.kieler.core.kgraph.KEdge
 import de.cau.cs.kieler.core.kgraph.KNode
 import de.cau.cs.kieler.core.krendering.KRenderingFactory
 import de.cau.cs.kieler.core.krendering.LineStyle
@@ -11,12 +12,18 @@ import de.cau.cs.kieler.core.krendering.extensions.KNodeExtensions
 import de.cau.cs.kieler.core.krendering.extensions.KPolylineExtensions
 import de.cau.cs.kieler.core.krendering.extensions.KPortExtensions
 import de.cau.cs.kieler.core.krendering.extensions.KRenderingExtensions
+import de.cau.cs.kieler.kiml.options.Direction
+import de.cau.cs.kieler.kiml.options.LayoutOptions
+import de.cau.cs.kieler.klay.layered.p4nodes.bk.CompactionStrategy
+import de.cau.cs.kieler.klay.layered.properties.Properties
+import de.cau.cs.kieler.klighd.SynthesisOption
 import de.cau.cs.kieler.klighd.syntheses.AbstractDiagramSynthesis
 import de.cau.cs.kieler.klighd.util.KlighdProperties
+import java.util.List
 import javax.inject.Inject
 import teetime.configuration.dsl.config.Configuration
 import teetime.configuration.dsl.config.Stage
-import teetime.configuration.dsl.config.ConfigurationElement
+import teetime.configuration.dsl.config.Connection
 
 class ConfigurationDiagramSynthesis extends AbstractDiagramSynthesis<Configuration> {
 
@@ -30,40 +37,183 @@ class ConfigurationDiagramSynthesis extends AbstractDiagramSynthesis<Configurati
 	@Inject extension KColorExtensions
 	extension KRenderingFactory = KRenderingFactory.eINSTANCE
 
+	private static val SynthesisOption SHOW_STATE = SynthesisOption::createCheckOption("Stage state", true)
+	private static val SynthesisOption SHOW_THREADS = SynthesisOption::createCheckOption("Thread assignment", true)
+
+	private val colorings = <Stage, KNode>newHashMap
+	private val falseStages = <Stage>newHashSet
+	private var List<Pipe> pipes
+
+	override public getDisplayedSynthesisOptions() {
+		return newLinkedList(
+			SynthesisOption::createSeparator("Visualization options"),
+			SHOW_STATE,
+			SHOW_THREADS
+		);
+	}
 
 	override KNode transform(Configuration model) {
+//        val root = model.createNode().associateWith(model);
+//        
+//        // Your dsl element <-> diagram figure mapping goes here!!
+//        for(ConfigurationElement ce : model.elements){
+//        	if(ce instanceof Stage){
+//        		System::err.println(ce)
+//        		root.children += ce.transformStage(model)
+//        	}
+//        }
+//        return root;
+		pipes = connections2Pipes(model.elements.filter(typeof(Connection)))
 		val root = model.createNode().associateWith(model);
+		var KNode color
+		val stages = model.elements.filter(typeof(Stage))
 
-        // Your dsl element <-> diagram figure mapping goes here!!
-        for(ConfigurationElement ce : model.elements){
-        	if(ce instanceof Stage){
-        		System::err.println(ce)
-        		root.children += ce.transformStage(model)
+		for (stage : stages) {
+			if (stage.inputPorts.size == 0 || stage.isActive) {
+				color = createThreadNode(root)
+				paintStages(stage, color)
 			}
 		}
+
+		stages.forEach [
+			val node = transformStage(model)
+			if (SHOW_THREADS.booleanValue) {
+				colorings.get(it).children += node
+			} else {
+				root.children += node
+			}
+		]
+
+		root.setLayoutOption(LayoutOptions::DIRECTION, Direction::RIGHT)
+		root.addLayoutParam(Properties::COMPACTION_STRATEGY, CompactionStrategy::IMPROVE_STRAIGHTNESS)
+
 		return root;
 	}
 
+	private def List<Pipe> connections2Pipes(Iterable<Connection> conns) {
+		val tempPipes = <Pipe>newLinkedList()
+		for (co : conns) {
+			if (co.middleStages.size == 0) {
+				tempPipes.add(new Pipe(co.startStage.startStageId, co.finalStage.startStageId))
+			} else {
+				tempPipes.add(new Pipe(co.startStage.startStageId, co.middleStages.head.startStageId))
+				for (i : 1 ..< co.middleStages.size) {
+					tempPipes.add(new Pipe(co.middleStages.get(i-1).startStageId, co.middleStages.get(i).startStageId))
+				}
+				tempPipes.add(new Pipe(co.middleStages.last.startStageId, co.finalStage.startStageId))
+			}
+		}
+		return tempPipes
+	}
+
 	private def create node : stage.createNode() transformStage(Stage stage, Configuration model) {
 		node.associateWith(stage);
 		node.addRoundedRectangle(4, 4, 1) => [
 			it.setShadow("black".color, 3)
-			val text = it.addText(stage.id).associateWith(stage.id).setSurroundingSpace(8, 0, 8, 0) => [
+			val text = it.addText(stage.name).associateWith(stage.name).setSurroundingSpace(8, 0, 8, 0) => [
 				it.setProperty(KlighdProperties.VISIBILITY_SCALE_LOWER_BOUND, 0.70);
 			]
-//			if (!(stage.active != "" || stage.inputPorts.size == 0) && SHOW_STATE.booleanValue) {
-//				it.lineStyle = LineStyle::DASH
-////				it.lineWidth = 2
-////				text.foreground = "gray40".color
-//				text.fontItalic = true
-////				foreground = "gray40".color
-//			}
+			if (!(stage.active) && SHOW_STATE.booleanValue) {
+				it.lineStyle = LineStyle::DASH
+//				it.lineWidth = 2
+//				text.foreground = "gray40".color
+				text.fontItalic = true
+//				foreground = "gray40".color
+			}
 //			if (falseStages.contains(stage)) {
 //				it.background = "#FF5555".color
 //			}
 		]
 		node.setMinimalNodeSize(100, 50)
-//		val outgoingPipes = stage.outputPorts.map[it.pipe]
-//		node.outgoingEdges.addAll(outgoingPipes.map[transformPipe(model)])
+		val outgoingPipes = stage.outputPorts
+		node.outgoingEdges.addAll(outgoingPipes.map[transformPipe(model)])
+	}
+
+	private def KNode createThreadNode(KNode root) {
+		val node = createNode
+		if (SHOW_THREADS.booleanValue) {
+			node.setLayoutOption(LayoutOptions::DIRECTION, Direction::RIGHT)
+			node.addLayoutParam(Properties::COMPACTION_STRATEGY, CompactionStrategy::IMPROVE_STRAIGHTNESS)
+			node.addRectangle() => [
+				background = "lightgray".color
+			]
+			root.children += node
+		}
+		node
+	}
+
+	private def KEdge transformPipe(Pipe pipe, Configuration model) {
+		val edge = pipe.createEdge.associateWith(pipe)
+		if (pipe.isInterThread && SHOW_THREADS.booleanValue) {
+			val sourceThreadNode = colorings.get(pipe.targetStage)
+			val sourceThreadPort = createPort => [
+				sourceThreadNode.ports += it;
+			]
+
+			val targetThreadNode = colorings.get(pipe.targetStage)
+			val targetThreadPort = createPort => [
+				targetThreadNode.ports += it;
+			]
+
+			edge.addPolyline(1)
+			edge.target = sourceThreadNode
+			edge.targetPort = sourceThreadPort
+
+			createEdge => [
+				source = sourceThreadNode
+				sourcePort = sourceThreadPort
+				sourceThreadPort.edges += it
+				addPolyline(1)
+				target = targetThreadNode
+				targetPort = targetThreadPort
+//				target = transformStage(pipe.targetPort.eContainer as Stage, model)
+			]
+
+			createEdge => [
+				source = targetThreadNode
+				sourcePort = targetThreadPort
+				targetThreadPort.edges += it
+				addPolyline(1).addHeadArrowDecorator
+				target = transformStage(pipe.targetStage, model)
+			]
+		} else {
+			edge.addPolyline(1).addHeadArrowDecorator
+			edge.target = transformStage(pipe.targetStage, model)
+		}
+		return edge
+	}
+
+	private def void paintStages(Stage stage, KNode color) {
+		if (colorings.containsKey(stage)) {
+			if(colorings.get(stage) != color) falseStages.add(stage)
+//				throw new IllegalArgumentException("Invalid thread assignment - " + stage.id + " needs to be active.")
+			return
+		} else {
+			colorings.put(stage, color)
+			stage.outputPorts.forEach [
+				if (!it.targetStage.isActive) {
+					paintStages(it.targetStage, color)
+				}
+			]
+		}
+	}
+
+	private def Boolean isInterThread(Pipe pipe) {
+		val first = pipe.sourceStage
+		val second = pipe.targetStage
+		return colorings.get(first) != colorings.get(second)
 	}
+
+	private def List<Pipe> outputPorts(Stage stage) {
+		val result = <Pipe>newLinkedList()
+		result.addAll(pipes.filter[sourceStage == stage])
+		return result
+	}
+
+	private def List<Pipe> inputPorts(Stage stage) {
+		val result = <Pipe>newLinkedList()
+		result.addAll(pipes.filter[targetStage == stage])
+		return result
+	}
+
 }